Clocking of data into registers is well-known in the art. A conventional high-speed register implementation is illustrated in block form in FIG. 1. Referring to FIG. 1, a register 10 is connected to receive data, via a two-to-one data selector 12, in response to rising edge transitions of a system clock signal, CK1. The two-to-one data selector 12 selects between recirculated data 14, recirculated from the register 10, and externally provided data 16 in response to an enable signal, EN. In particular, when the enable signal, EN, is low, the recirculated data 14 is clocked into the register 10. When the enable signal, EN, is high, the externally supplied data 16 is clocked into the register 10.
It can be seen that the register 10 is clocked even when no data is being provided externally. Since it is not desired to change the contents of the register 10 when no data is being provided externally (and, in fact, the contents are not being changed), the register 10 is unnecessarily clocked in this situation, and power is unnecessarily consumed.
There have been attempts to implement "gated" register clocking circuits. With gated register clocking, a register is clocked only when it is desired to change the contents of the register. However, these circuits typically require strict control of set-up and hold times. Particularly in high frequency applications, clock skewing may cause violation of the strict set-up and hold time requirements.